NVIDIA builds the world's largest chips. As the chip size grows larger and larger, power efficiency become more and more important, whether the chip is used in datacenter, in cars, or in PCs. We design a PMU IP starting from 13y ago to help making the chip always working in the best efficient way for both idle scenarios and active scenarios. The PMU IP is composed by a RISC-V core and various of custom designed control logics. The HW logic collects the status from the entire chip, processing the data, and co-work with SW running on the RISC-V core to determine the best operation point. As the PMU design becomes more and more complicated and used in more and more chips, we are hiring a ASIC Design Engineer to help building a more powerful PMU.

What you'll be doing:

• Co-work with the IP architect and designer to define the IP verification methodology and test plan. Finishing the IP verification for all new coming features from project to project.

• Maintain and improve the SV based unit-level TB to be power powerful and efficient. Maintain the regression and run various of sing-off verification checklists.

• Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.

What we need to see:

• Pursuing MS degree from EE/CS or related majors

• Self-driving, active thinking and problem solving.

• Familiar with perl or python script. Familiar with C/C++ coding.

• Willing to learn and contribute in the internship.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!