THE ROLE: 

The Product Development Engineer position is in the Software, Productivity and Customer Success group, located in Longmont, CO, for an highly experienced, autonomous and motivated engineer to focus on next generation HW/SW architecture enablement, tools specification, validation, documentation, and key customer’s support. 

THE PERSON: 

The successful candidate will work closely with the AMD tools R&D team, HW architecture and design teams, and Marketing/Applications teams to capture key market requirements and key customer use models to validate the technology roadmap, schedule and priorities. The candidate will leverage his technical experience to demonstrate the benefits and tradeoffs of HW modeling versus tools support options, with focus on test equipment, emulation and prototyping markets to influence the overall solution. The candidate will present his work to cross-functional teams and senior management on regular basis. 

KEY RESPONSIBILITIES: 

• Specifying and tracking SW product features to enable new FPGA and Adaptive SoC devices for the current and future device families. Work with internal HW/SW cross-functional teams on dependencies, schedule alignment and productivity during the early development phases. This includes occasional architecture benchmarking and feedback during the definition phases. 

• Contributing to the SW releases content definition, specifications, early testing of new and updated features, with focus on complex features requiring knowledge across HW and SW domains or requiring alignment of several SW teams. 

• Working with the field team, SW engineering and junior product engineers on Tier-1 customers, including Emulation-Prototyping vendors end users. 

• Interfacing with Senior Management, Quality, Tech Marketing and Application teams to call out risks, report on selected KPIs, ensure issues are resolved and corrective actions completed. 

• Developing and delivering training materials on new features and methodologies. Authoring high quality documentation tuned to the needs of the reader for their areas and levels of expertise. 

• Actively exploring innovative flows, methodologies and analysis techniques aimed at scaling and productivity, internally. Staying current with and proposing the internal use of industry approaches, algorithms, and practices. 

REQUIRED EXPERIENCE: 

• Customer Awareness: Working knowledge of end-to-end RTL-based design flows and associated tool chain expectations. 

• Product Knowledge: Excellent working knowledge of the entire FPGA or ASIC design process and tool flow, with in-depth expertise in timing analysis and closure. Has expertise in: HDL, scripting (Tcl/Python), timing and physical design constraints (SDC/XDC), synthesis/placement/routing/verification tools. 

• Technology Enablement: 5 years’ experience in enabling new devices and technologies from R&D teams to FPGA or Adaptive SoC end customers by identifying, specifying, documenting new features and new flows. 

• Problem Solving: Ability to handle and solve complex system level issues, internally and with tier-1 customers, by identifying proper escalation paths, defining relevant experiments, driving workarounds and issues resolution to meet customers’ schedule. 

• Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear while exposing only necessary information to compilation tools users and end customers. 

ACADEMIC CREDENTIALS: 

• Master of Science or equivalent work experience in Electrical Engineering or similar technology area, with minimum 15 years of relevant experience. 

LOCATION: Longmont, CA  

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