IP Design Architect / Micro-Architect
Intel Corporation
Penang, Malaysia
Job posting number: #7274543 (Ref:JR0267338)
Posted: August 21, 2024
Job Description
Job Description
In Q4 2023, Intel announced PSG will be reported as a separate business unit beginning on January 1, 2024 with ongoing support from Intel. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.Altera is Poised To...
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Altera FPGAs offer a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and built-in intellectual property (IP). All these combined with the outstanding software tools lower FPGA development time, power, and cost for enabling product differentiation. Differentiation of your product from others is the difference from survival to prosperity.
Configurable FPGAs will require multiple IPs to form a complete system design for different FPGA devices. Thus, the need to have scalable IP architectures, micro-architectures and designs are necessary to optimize the development efficiency.
As the design architect/micro-architect, you get to explore and define the complex IP features for implementation feasibility by working with the stakeholders from both hardware and software domains. You always perform design trade-off to achieve the optimal modularity, scalability and fabric PPU (power, performance and utilization). You review the IP requirements and come up the design implementation strategy for the IP. You implement logic design in Register Transfer Level (RTL) code, carry out logic simulation and apply corrective measures for simulation failures. You also analyze and use lint results to improve design sign-off. Design review and peer review shall be driven by you for quality purpose.
In this position you will work closely with the design verification team in determining the proper validation strategy for the IP, and defining and providing feedback on the hardware validation plans. You also work with post-silicon validation team to resolve silicon level sightings, and drive any paradigm shifts needed in design execution including FPGA development flow and process. As a technical leader you provide technical guidance to junior engineers.
Qualifications
Minimum Qualifications� Bachelor of Science degree or Master of Science degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science.
� At least 15 years of experience in designing FPGAs, SoCs or IP blocks.
� In depth knowledge of RTL language such as System Verilog, Verilog or VHDL.
� In depth knowledge of industry standard tools and methods such as Synopsys VCS, Mentor/Siemens Questasim, Cadence Xcelium, etc.
� Excellent technical leadership skills, and a proven ability to work with dynamic schedules
Preferred Qualifications
� Knowledge of 5G (O-RAN, eCPRI, Front-Haul Compression, JESD) protocols and usage models.
� Knowledge of object-oriented programming in TCL, Java, Python, or some other languages.
� Behavioral traits including but not limited to strong communication skills (written and verbal), tolerance of ambiguity, problem solving, teamwork, attention to detail, commitment to task, and quality focus.
� Experience with FPGA SW development platform especially on Altera Quartus Pro.
� Experience in system interconnect bus such as AXI, AHB, AVMM, etc.
� Knowledge in Agile development and familiar with Scrum process.